1. Field of the Invention
This invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to the implantation of impurities into the sidewalls of an active region.
2. Description of the Related Art
A semiconductor memory device requires not only memory cell transistors but also peripheral transistors constituting a power generating circuit, a decoder circuit, and the like.
The peripheral transistors include low-voltage MOS transistors which use, for example, a voltage VDD (e.g. 1.5V) as a power supply voltage and high-voltage MOS transistors which use, for example, a voltage VPP (e.g., 20V), which is higher than the power supply voltage of the low-voltage MOS transistors, as a power supply voltage.
In the processes of manufacturing peripheral transistors, the process of forming element isolating regions which electrically isolate the peripheral transistors begins with the step of making trenches. A method of using RIE (reactive ion etching) in the step has been disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 10-4137.
However, in the process of performing RIE, there arise such problems as damage to the sidewall of the active region and the storage of positive charge at the interface of the active region. As the elements are miniaturized further, the effect of these problems cannot be ignored. That is, as the miniaturization proceeds, the sidewall of the active region is more liable than the area directly under the gate to be reversed into the on state, even at a low voltage, with the result that the leakage current flowing in the sidewall of the active region increases. The effect appears significantly in a high-voltage n-type MOS transistor which uses a p-well region with a relatively low impurity concentration or a p-type semiconductor substrate.